Memory Modeling

Ternary CAM (TCAM) Power and Delay Modeling

Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these search primitives on network processors, general purpose machines, and even custom ASICs. However, supporting these applications with standard memories requires very careful analysis of access patterns, and achieving worst case performance can be quite difficult and complex. A simple solution is often possible if a Ternary CAM is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. We examine the structure inside a modern TCAM and present a simple, yet accurate, power model. We also provide support to estimate the dynamic power consumption of a large TCAM. We validate the model using industrial TCAM datasheets and prior published works. This model can be used to explore new hybrid TCAM-SRAM algorithms that have the potential to address the growing problem of power management in next-generation network devices.
Source code
You can download the source code at this link TCAM Delay and Power Model.

Changes:
   Version 1.0
      - Initial model for dynamic search power and access time

  Version 2.0
     - Adding the sub-threshold leakage power analysis
     - Adding the support of read/write power
     - Including wire features from ITRS roadmap for future technologies
Publications