//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.


//----------------------------------------------------
//File Name: mux_4_1.v
//Function: a simple 4x1 mux
//Coder: Brett Brotherton (brett.brotherton@gmail.com)
//----------------------------------------------------

module  mux_4_1(i0, i1, i2, i3, sel, mux_out);

//-----------Input Ports---------------
input[7:0] i0, i1, i2, i3;
input[1:0] sel;
//-----------Output Ports---------------
output[7:0] mux_out;
//------------Internal Variables--------
reg[7:0]  mux_out;
//-------------Code Starts Here---------
always @ (sel or i0 or i1 or i2 or i3)
begin : MUX
 case(sel ) 
    2'b00 : mux_out = i0;
    2'b01 : mux_out = i1;
    2'b10 : mux_out = i2;
    2'b11 : mux_out = i3;
 endcase 
end

endmodule //End Of Module mux