//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

//----------------------------------------------------
//File Name: ram.v
//Function: a synchronous read/write ram for the AC State machine tile
//Coder: Brett Brotherton (brett.brotherton@gmail.com)
//----------------------------------------------------
module ram( clk, address, rdaddress, data_in, data_out, we);

//inputs
input clk;
input[7:0] address;
input[7:0] rdaddress;
input[47:0] data_in;
input we;


//outputs
output[47:0] data_out;
//reg[DATA_WIDTH-1:0] data_out;

//internal variables
reg [47:0]mem[256:0];
reg [7:0] read_add;

//code starts here
//mem write operation
always @ (posedge clk)
begin
	if (we) begin
		mem[address] <= data_in;
		read_add <= rdaddress;
	end
	else begin
		read_add <= rdaddress;
	end
end

assign data_out = mem[read_add];


endmodule //End of Module ram