//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.


Readme - String Match Engine (SME) 

Author: Brett Brotherton, Tim Sherwood


Description:
Synthesizable verilog description of a hardware module for high speed string matching.
It is based on a modified version of the Aho-Corasik algorithm published by Tan and
Sherwood in ISCA'05.  For a more detailed description of the string match 
engine go to http://www.cs.ucsb.edu/~sherwood/pubs/ISCA-string.pdf.  This release does
not include any of the glue logic to interface these string matching modules with
the rest of the system, as those will be highly dependent on the particular hardware
platform you are using.  This code is very memory-centric, and synthesis results are
signficantly impacted by the details of the memories used.  If you are prototyping on
FPGAs we recommend that you double check that the tiles map to block-ram (or equivelent type)
memories.  For full custom designs, a memory compiler should be used.

Source Files:

HDL Files:

- mux_4_1.v: simple 4 to 1 mux used in the design.

- tile_mem.v: Altera generated RAM that has 256 48 bit words.  

- ram.v: general description of RAM that can be used with non Altera boards that
  will not support the megafunctions used in tile_mem.v

- tile.v: implementation of tile for the rule modules, each rule module has 4 tiles

- rule_module.v: rule module for string match engine

- string_match_engine.v: string match engine, contains multiple rule modules and 
  outputs matches in an easy to handle manner