//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.


//----------------------------------------------------
//File Name: rule_module.v
//Function: a rule module for AC string comparison, on module can handle 16 rules
//Coder: Brett Brotherton (brett.brotherton@gmail.com)
//----------------------------------------------------

module rule_module(clk, rst, data_enable, byte1, f_match_vector, address, we, config_data);
//width of sme vector
parameter VECTOR_WIDTH = 16;
//width of memeory
parameter DATA_WIDTH = 48;
//address width of memory
parameter ADDRESS_WIDTH = 8;

//inputs
input clk, rst;
input data_enable;
//write enable
input we;
//input for AC state machine
input[7:0] byte1;
//data to be written to the tile for initialization and updates
input[DATA_WIDTH-1:0] config_data;
//address to write the data to extra two bits are for the rule module selection
input[2+ADDRESS_WIDTH-1:0] address;

//outputs
//full match vector (intersection of partial match vectors)
output[VECTOR_WIDTH-1:0] f_match_vector;
reg[VECTOR_WIDTH-1:0] f_match_vector;

//internal variables
wire[VECTOR_WIDTH-1:0] v0, v1, v2, v3; //wires to connect rule module to and gate
wire[3:0] w; //write signals for tiles


//code starts here
//using the write signal determines which tile should be written to
assign w = (we) ? (4'h1 << address[2+ADDRESS_WIDTH-1:2+ADDRESS_WIDTH-2]) : 4'b0;

//initialization and assignment of full match  vector
always @ (v0 or v1 or v2 or v3 or rst or f_match_vector or we)
begin
	if (rst || we ) begin
		//initialize to zero when reseting or writing
		f_match_vector = 8'h00;
	end
	else begin
		//otherwise match vector is intersection of partial match vector 
		//stores all matches until module is reset for the next packet
		f_match_vector = (v0 & v1 & v2 & v3) | f_match_vector;
	end
end

//mapping of tiles to the rule module
//each rule moduel has 4 tiles
tile tile_0( .clk(clk), .rst(rst), .data_enable(data_enable), .config_data(config_data), .data_in(byte1[7:6]), .match_vector(v0), .address(address[ADDRESS_WIDTH-1:0]), .write(w[0]));

tile tile_1( .clk(clk), .rst(rst), .data_enable(data_enable), .config_data(config_data), .data_in(byte1[5:4]), .match_vector(v1), .address(address[ADDRESS_WIDTH-1:0]), .write(w[1]));

tile tile_2( .clk(clk), .rst(rst), .data_enable(data_enable), .config_data(config_data), .data_in(byte1[3:2]), .match_vector(v2), .address(address[ADDRESS_WIDTH-1:0]), .write(w[2]));

tile tile_3( .clk(clk), .rst(rst), .data_enable(data_enable), .config_data(config_data), .data_in(byte1[1:0]), .match_vector(v3), .address(address[ADDRESS_WIDTH-1:0]), .write(w[3]));



endmodule    // end rule_module