//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.


//----------------------------------------------------
//File Name: string_match.v
//Function: string match hardware containing multiple rule modules
//Coder: Brett Brotherton (brett.brotherton@gmail.com)
//----------------------------------------------------

module string_match_engine( clk, rst, byte_in, data_enable, config_data, address, we, vector_sel, match_vectors, match_flags);

//number of tiles in sme
parameter NUM_TILES = 4
;
//number of bits for write signal
//should be log2(NUM_TILES)
parameter WRITE_BITS = 2;

parameter VECTOR_WIDTH = 16; 
parameter DATA_WIDTH = 48;
parameter ADDRESS_WIDTH = 8;
//inputs
//clock, reset, and write enable for memory
input clk, rst, we;
//data_enable is the signal to take in data
input data_enable;
//input for matching engine
input[7:0] byte_in;
//address for writing to rule module (has format of {module address, tile address, mem address})
input[ADDRESS_WIDTH+2+WRITE_BITS-1:0] address;
//data to write for initialization and update of rule modules
input[DATA_WIDTH-1:0] config_data;
//select which vector to output
input[WRITE_BITS-1:0] vector_sel;
//outputs
output[VECTOR_WIDTH-1:0] match_vectors;
reg[VECTOR_WIDTH-1:0] match_vectors;
//flags that get set off if there is a match in one of the engines
output[NUM_TILES-1:0] match_flags;
reg[NUM_TILES-1:0] match_flags;

//internal signals
//vectors to map from rule modules to match vector output
wire[15:0] v0, v1, v2, v3;
//address to write to for initialization and updates of rule modules
wire[ADDRESS_WIDTH+2-1:0] write_address;
//address of module to write to
wire[WRITE_BITS-1:0] write_mod;

//map output to the individual vectors

always @ (vector_sel or v0 or v1 or v2 or v3 )
begin
  case (vector_sel)
    0 : match_vectors = v0;
    1 : match_vectors = v1;
    2 : match_vectors = v2;
    3 : match_vectors = v3;
    default : match_vectors = 0;
  endcase
end

//map address to separate address parts
assign write_mod = address[ADDRESS_WIDTH+2+WRITE_BITS-1:ADDRESS_WIDTH+2];
assign write_address = address[ADDRESS_WIDTH+2-1:0];

//decoder to set macth_flags
integer i ; 
always @ (v0 or v1 or v2 or v3 )
begin
if (v0 == 16'h0000) begin
  match_flags[0] <= 1'b0;
end else begin
  match_flags[0] <= 1'b1;
end
if (v1 == 16'h0000) begin
  match_flags[1] <= 1'b0;
end else begin
  match_flags[1] <= 1'b1;
end
if (v2 == 16'h0000) begin
  match_flags[2] <= 1'b0;
end else begin
  match_flags[2] <= 1'b1;
end
if (v3 == 16'h0000) begin
  match_flags[3] <= 1'b0;
end else begin
  match_flags[3] <= 1'b1;
end
end


//decoder for writing to different tiles of different rule modules
//write_mod selects which module to write to and write_tile has the enable
//and tile select for writing to that module
wire[NUM_TILES-1:0] decoder_out;
assign decoder_out = (we) ? (1 << write_mod) : 0 ;

//mapping of the string match engine to tiles

rule_module rm_0(.clk(clk), .rst(rst), .data_enable(data_enable), .byte1(byte_in), .f_match_vector(v0), .address(write_address), .we(decoder_out[0]), .config_data(config_data));
rule_module rm_1(.clk(clk), .rst(rst), .data_enable(data_enable), .byte1(byte_in), .f_match_vector(v1), .address(write_address), .we(decoder_out[1]), .config_data(config_data));
rule_module rm_2(.clk(clk), .rst(rst), .data_enable(data_enable), .byte1(byte_in), .f_match_vector(v2), .address(write_address), .we(decoder_out[2]), .config_data(config_data));
rule_module rm_3(.clk(clk), .rst(rst), .data_enable(data_enable), .byte1(byte_in), .f_match_vector(v3), .address(write_address), .we(decoder_out[3]), .config_data(config_data));


endmodule

//Created with Brett's Perl script