//  UC Santa Barbara ArchLab
//  String Match Engine HDL - Release 0.8
//
// Copyright (c) 2005 The Regents of the University of California.
// All Rights Reserved.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes,
// without fee, and without a written agreement is hereby granted,
// provided that the above copyright notice, this paragraph and the
// following three paragraphs appear in all copies.
//
// Permission to incorporate this software into commercial products may
// be obtained by contacting the University of California. For
// information about obtaining such a license contact:
// Tim Sherwood <sherwood@cs.ucsb.edu>
//
// This software program and documentation are copyrighted by The Regents
// of the University of California. The software program and
// documentation are supplied "as is", without any accompanying services
// from The Regents. The Regents does not warrant that the operation of
// the program will be uninterrupted or error-free. The end-user
// understands that the program was developed for research purposes and
// is advised not to rely exclusively on the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY
// FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
// INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND
// ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS"
// BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.


//----------------------------------------------------
//File Name: tile.v
//Function: a tile for the AC state machine
//Coder: Brett Brotherton (brett.brotherton@gmail.com)
//----------------------------------------------------

module tile(clk, rst, data_enable, config_data, data_in, match_vector, address, write);
//width of data memory
parameter DATA_WIDTH = 48;
//width of partial match vector
parameter VECTOR_WIDTH = 16;
//width of data address
parameter ADDRESS_WIDTH = 8;

//inputs
input clk;
input rst;
input data_enable;
//data to be written to the tile for initialization and updates
input[DATA_WIDTH-1:0] config_data;
//address to write the data to
input[ADDRESS_WIDTH-1:0] address;
//write enable 
input write;
//input for AC state machine
input[1:0] data_in;

//outputs
//partial match vector
output[VECTOR_WIDTH-1:0] match_vector;

//internal variables
//wire to connect mux to current_state (output of mux is next state)
wire[7:0] mux_out; 
//wire to connect mem to mux and match vector
wire[DATA_WIDTH-1:0] mem_out;
//current state of AC state machine
reg[7:0] current_state;
//makes sure only one state change per byte of data
reg state_change;
//code begins here

//handle state transition
//change states only on rising clock edge
always @ (posedge rst or posedge write or posedge clk)
begin : INITIALIZATION
	//handle reset of machine
	if ((rst)||(write)) begin
		//reset state and stall variables
		current_state <= 8'h00;
		state_change <= 1'b1;
	end
	//We don't want to change states when we are writing to memory
	else if (data_enable & state_change) begin
		//if enable is set (we are reading in data) then goto next cycle
		current_state <= mux_out;
		state_change <= 1'b0;
	end
	else if (data_enable & state_change == 1'b0) begin
		state_change <= 1'b1;
	end
	//otherwise enable not set so do nothing (stay in current state)
end

//map match vector to LS 16 bits of the memory output
assign match_vector = mem_out[15:0];

supply1 vcc;
//now lets add other modules and connect them together
//connect the tile to memory for storing state machine data
tile_mem ram0(.data(config_data), .wren(write), .wraddress(address), .rdaddress(current_state), .clock(clk), .q(mem_out));
//ram ram0(.enable(vcc), .clk(clk), .address(address), .rdaddress(current_state), .data_in(config_data), .data_out(mem_out), .we(write));
//hook up mux to determine next state
mux_4_1 mux0(.i0(mem_out[47:40]), .i1(mem_out[39:32]), .i2(mem_out[31:24]), .i3(mem_out[23:16]), .sel(data_in), .mux_out(mux_out));			

		
endmodule //End the tile module