Journal Articles

  1. Peter R. Cappello and Kenneth Steiglitz.A VLSI Layout for a Pipelined Dadda Multiplier. ACM Trans. on Computer Systems, 1(2):157--174, May 1983 (reprinted as a book chapter).
  2. Peter R. Cappello and Kenneth Steiglitz. Completely Pipelined Architectures for Digital Signal Processing. IEEE Trans. on Acoust., Speech, Signal Processing, 31(4):1016--1023, Aug. 1983.
  3. Peter R. Cappello, Andrea LaPaugh, and Kenneth Steiglitz. Optimal Choice of Intermediate Latching to Maximize Throughput in VLSI Circuits. IEEE Trans. on Acoust., Speech, Signal Processing, 32(1):28--33, Feb. 1984.
  4. Peter R. Cappello and Kenneth Steiglitz. Some Complexity Issues in Digital Signal Processing. IEEE Trans. on Acoust., Speech, Signal Processing, 32(5):1037--1041, Oct. 1984.
  5. Peter R. Cappello and Kenneth Steiglitz. Unifying VLSI Array Design with Linear Transformations of Space-Time. In Franco P. Preparata, editor, Advances in Computing Research, vol. 2: VLSI Theory, pages 23--65, JAI Press, Inc., Greenwich, CT, 1984.
  6. Peter R. Cappello and Kenneth Steiglitz. A Note on Free Accumulation in VLSI Filter Architectures. IEEE Trans. on Circuits Syst., CAS-32(3):291--296, Mar. 1985.
  7. Peter R. Cappello. Gaussian Elimination on a Hypercube Automaton. J. Parallel and Distributed Computing, 4(3):288--308, June 1987.
  8. Peter R. Cappello and Cheng-Wen Wu. Computer-Aided Design of VLSI FIR Filters. Proc. IEEE, 75(9):1260--1271, Sep. 1987 (also translated into Russian).
  9. Cheng-Wen Wu and Peter R. Cappello. Application-Specific CAD of VLSI Second-Order Sections. IEEE Trans. Acoust., Speech, Signal Processing, 36(5):813--825, May 1988.
  10. Peter R. Cappello and Alan J. Laub. Systolic Computation of Multivariable Frequency Response. IEEE Trans. Autom. Control, 33(6):550--558, June 1988.
  11. Peter R. Cappello and Willard L. Miranker. Systolic Super Summation. IEEE Trans. Comput., 37(6):657--677, June 1988.
  12. Grant Davidson, Peter R. Cappello, and Allen Gersho.Systolic Architecture for Vector Quantization. IEEE Trans. Acoust., Speech, Signal Processing, 36(10):1651--1664, Oct. 1988 (reprinted as a book chapter).
  13. Cheng-Wen Wu and Peter R. Cappello. Block Multipliers Unify Bit-Level Cellular Multiplication. Intl. J. Computer Aided VLSI Design, 1(1):113--125, July 1989.
  14. Bradley R. Engstrom and Peter R. Cappello. The SDEF Programming System. J. Parallel and Distributed Computing, 7:201--231, 1989.
  15. Yoav Yaacoby and Peter R. Cappello. Scheduling a System of Nonsingular Affine Recurrence Equations onto a Processor Array. J. VLSI Signal Processing, 1(2):115--125, 1989.
  16. Cheng-Wen Wu and Peter R. Cappello. Easily Testable Iterative Logic Arrays. IEEE Trans. Comput., 39(5):640--652, May 1990.
  17. Peter R. Cappello, Efstratios Gallopoulos, and Çetin K. Koç. Systolic Computation of Interpolating Polynomials. Computing, 45:95--118, 1990.
  18. Çetin K. Koç, Peter R. Cappello, and Efstratios Gallopoulos. Decomposing Polynomial Interpolation for Systolic Arrays. Int. J. Computer Mathematics, 38:219--239, 1991.
  19. Peter R. Cappello. A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms. IEEE Trans. Parallel and Distributed Systems, 3(1):4--13, Jan. 1992.
  20. Peter R. Cappello and Willard L. Miranker. Systolic Super Summation with Reduced Hardware. IEEE Trans. Comput., 41(3):339--342, March 1992.
  21. Chris J. Scheiman and Peter R. Cappello. A Processor-Time-Minimal Systolic Array for Transitive Closure. IEEE Trans. on Parallel and Distributed Systems, 3(3):257--269, May 1992.
  22. Yoav Yaacoby and Peter R. Cappello. Decoupling the Dimensions of a System of Affine Recurrence Relations. Linear Algebra and Its Applications, 167:157--170, April 1992.
  23. Çetin K. Koç and Peter Cappello. Systolic Arrays for Integer Chinese Remaindering. Parallel Computing, 19:1303--1311, 1993.
  24. Chris J. Scheiman and Peter Cappello. A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms. IEEE Trans. on Parallel and Distributed Systems, 5(3): 274 -- 280, Mar. 1994.
  25. Yoav Yaacoby and Peter Cappello. Bounded Broadcast in Systolic Arrays. Int. J. of High Speed Computing, 6(2):223-237, 1994.
  26. John Bruno and Peter R. Cappello. Implementing the 3D Alternating Direction Method on the Hypercube. J. Parallel and Distributed Computing, 23:411--417, 1994.
  27. Yoav Yaacoby and Peter Cappello. Converting Affine Recurrence Equations to Quasi-Uniform Recurrence Equations. Magdy Bayoumi, Editor, J. of VLSI Signal Processing, 11:1 & 2, pp. 113-131, Oct. 1995.
  28. Chris J. Scheiman and Peter Cappello. A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms. Parallel Processing Letters, 6(4):539-550, Dec. 1996.
  29. Bernd O. Christiansen, Peter Cappello, Mihai F. Ionescu, Michael O. Neary, Klaus E. Schauser, and Daniel Wu. Javelin: Internet-Based Parallel Computing Using Java. Concurrency: Practice and Experience, 9(11): 1139 - 1160, Nov. 1997.
  30. Peter Cappello and Omer Egecioglu. Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems. International Journal of Foundations of Computer Science, 9(4):351-375, 1998, World Scientific Publishing Company.  Accepted for publication 20 November 1997.
  31. M. O. Neary, B. O. Christiansen, P. Cappello, and K. E. Schauser.  Javelin: Parallel computing on the internet.  Future Generation Computer Systems, Elsevier Science, Amsterdam, Netherlands, Vol.15(5-6):659-674, October 1999.
  32. M. O. Neary, S. P. Brydon. P. Kmiec, S. Rollins, and P. Cappello.  Javelin++: Scalability Issues in Global Computing.  Concurrency: Practice and Experience, 12:727 - 753, 2000. (Received 1 Aug 99. Revised 15 Nov 99. Accepted Nov 99. ) Full paper (ps | pdf).
  33. Peter Cappello, Omer Egecioglu, and Chris Scheiman.  Processor-time-optimal systolic arrays. Parallel Algorithms and Applications, 15:167 - 199, 2000.
  34. Peter Cappello and Dimitrios Mourloukos. CX: A Scalable, Robust Network for Parallel Computing. 10(2): 159 - 171, Scientific Programming Journal (Special Issue on Grid Computing, Ewa Deelman and Carl Kesselman, eds. ), 2002. BibTex. (http://iospress.metapress.com/link.asp?id=mwq0y3utf3nq)
  35. Michael O. Neary and Peter Cappello. Advanced Eager Scheduling for Java-Based Adaptively Parallel Computing. Concurrency and Computation: Practice and Experience, 2005, 17:797 - 819. Published online 23 February 2005 in Wiley Interscience (www.interscience.wiley.com). DOI: 10.1002/cpe.855. Received 15 Jan 03. Revised 31 Aug 03. Accepted 14 Oct 03.
  36. Peter Cappello. Application-Specific Processor Architecture: Then and Now. Journal of VLSI Signal Processing Systems. Springer. Accepted 22 Jun 07.