Peter Cappello Header image
Chapters Conference articles Journal Articles Patents Presentations

Presentations

This is a list of presentations other than those given at a conference with a published proceedings. In each item, the presentation was given by the author whose name is emboldened.

  1. (Invited) Peter Cappello. Unifying Systolic Design with Linear Transformations of Spacetime. Electrical Engineering-Systems Department Seminar, University of Southern California, Los Angeles, Feb. 1983.
  2. (Invited) Peter Cappello. Unifying Systolic Design with Linear Transformations of Spacetime. Office of Naval Research Workshop on VLSI Architectures for Special-purpose Machines, Mt. Ada Conference Center, Catalina, CA, Mar. 1984.
  3. (Invited) Peter Cappello. Mapping Gaussian Elimination onto Multiprocessor Architectures. Computer Science Department, Yale University, New Haven, CT, Aug. 1985.
  4. (Invited) Peter Cappello. Systolic Design for Digital Signal Processing. Symposium on the Impact of VLSI on Signal Processing, Communications Research Laboratory, McMaster University, Hamilton, Ontario, CANADA, Oct. 1985.
  5. (Selected) Peter Cappello. Solving Dense Linear Systems on a Hypercube Automaton. SIAM Conf. on Parallel Processing for Scientific Computing, Norfolk, VA, Nov. 1985.
  6. (Invited) Peter Cappello. An FIR Filter Tissue. Office of Naval Research Workshop on Ultra Submicron Architectures, Pasadena, Dec. 1985.
  7. (Invited) Peter Cappello. Systolic Design for Digital Signal Processing. IEEE Philadelphia Section Seminar on Systolic Parallel Architectures for Signal Processing, University of Pennsylvania, Apr. 1986.
  8. (Invited) Peter Cappello. Languages and Tools for Systolic Computation. Office of Naval Research Workshop on Systolic Algorithms and Architectures, Hilton Head, SC, Dec. 1986.
  9. (Invited) Peter Cappello. Representing Systolic Computation. Dept. of Electrical Engineering, UCLA, Nov. 1987.
  10. Peter Cappello. A New Bijection between Natural Numbers and Rooted Trees. 4th SIAM Conf. on Discrete Mathematics, San Francisco, June 1988.
  11. (Invited) Peter Cappello. A VLSI layout for a Dadda Multiplier. Computer Engineering Seminar, University of Southern California, Los Angeles, March 1989.
  12. Peter Cappello and Çetin K. Koç. Decomposing Chinese remaindering for systolic arrays. SIAM Ann. Meeting, San Diego, July 1989.
  13. Peter Cappello, Çetin K. Koç, and Efstratios Gallopoulos. Systolic computation of interpolating polynomials. SIAM Conf. on Parallel Processing for Scientific Computing, Chicago, Dec. 1989.
  14. (Invited) Peter Cappello. A Processor-Time Minimal Systolic Array for Matrix Product. Computer Science Colloquium, University of Oregon, Eugene, Apr. 1990.
  15. Yoav Yaacoby and Peter Cappello. Decoupling the dimensions of a system of affine recurrence equations. The 6th Haifa Matrix Theory Conference, The Technion, Haifa, ISRAEL, June 1990.
  16. Ömer Egecioglu and Peter Cappello. A Bijection with Applications to Asymptotic Properties of Rooted Trees. 6th SIAM Conf. on Discrete Mathematics, Vancouver, BC, June 1992.
  17. (Invited) Peter Cappello and Chris Scheiman. A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms. Electrical and Computer Engineering Seminar, Oregon State University, Corvallis, OR, Feb. 1993.
  18. (Invited) Peter Cappello. Javelin: Internet-Based Parallel Computing Using Java. National Tsing Hua University (NTHU), Hsinchu, TAIWAN, April, 1998.
  19. (Invited) Peter Cappello. Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems. National Tsing Hua University (NTHU), Hsinchu, TAIWAN, April, 1998.
  20. (Invited) Peter Cappello. Javelin: Internet-Based Parallel Computing Using Java. National Cheng Kung University (NCKU), Tainan, TAIWAN, April, 1998.
  21. (Invited) Peter Cappello. Javelin: Internet-Based Parallel Computing Using Java. National Taiwan University (NTU), Taipei, TAIWAN, April, 1998.
  22. (Invited) Peter Cappello. Java-Based Parallel Computing on the Internet: Javelin 2.0 & Beyond, Seminar on High Performance Computing and Java, International Conference and Research Center for Computer Science, Schloss Dagstuhl, GERMANY, Aug. 2000.
  23. (Invited) Peter Cappello. General Purpose Processors as Processor Arrays (abstract, slides), IEEE 17th Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), Steamboat Springs, CO, 2006.