Peter Cappello Header image

Professional Activity

JOURNAL

Editorial Board

  • Journal of VLSI Signal Processing, '88 -- present.
  • IEEE Transactions on Acoustics, Speech, and Signal Processing, '88 -- '90.

Referee

Acta Informatica
Advances in Computing Research
Automatica
BIT
Computing
IEE Proc. (G) Circuits, Devices and Systems
IEEE Journal of Solid-State Circuits
IEEE Proceedings
IEEE Trans. Circuits and Systems
IEEE Trans. Computers
IEEE Trans. Parallel and Distributed Systems
IEEE Trans. Signal Processing
Information Sciences
International Journal of Computer Aided VLSI Design
International Journal of Parallel Programming
International Journal of Science and Technology
Journal of Parallel and Distributed Computing
Journal of VLSI Signal Processing
Parallel Computing
Parallel Processing Letters

FUNDING ORGANIZATION

Member

NSF Review Panel for Research Initiation Awards, (Microelectronic Information Processing Systems Division), Washington.

Reviewer

Louisiana Board of Regents
MICRO
National Research Council (ARO)
National Science Foundation

CONFERENCE

Workshop Chair

  • IEEE Workshop on VLSI Signal Processing, USC, Los Angeles,'84.

Conference Co-Chair

  • IEEE Int. Conference on Application Specific Array Processors, Strasbourg, FRANCE, '95.

Technical Program Co-Chair

  • IEEE Int. Conference on Application Specific Array Processors, San Francisco, '94.

Program Committee Member

Session Chair

  • "Cluster Computing," IASTED Int. Conf. on Parallel and Distributed Computing and Systems, Phoenix, 2005.
  • "Web Services & Tools," IASTED Int. Conf. on Parallel and Distributed Computing and Systems, San Diego, 2003.
  • Joint  ACM  Java Grande - ISCOPE (Int. Symp. on Computing in Object-Oriented Parallel Environments), Seattle, Nov, 2002.
  • `Computer Arithmetic', Int. Conf. on Application Specific Array Processors (ASAP), San Jose, CA, 2002.
  • `Web Servers', International Workshop on Scalable Web Services, Toronto, CANADA, 2000.
  • `Efficient Design Methods I,' Int. Conf. on Application Specific Array Processors, Venice, ITALY '93.
  • `Short Presentations', IEEE Workshop on VLSI Signal Processing, Napa Valley, CA '92.
  • `Parallel Architecture,' Int. Conf. on Application Specific Array Processors, Oakland, CA '92.
  • `Computer Arithmetic,' IEEE Int. Conf. on Computer Design, Cambridge, MA '91.
  • `Algorithms,' IEEE Workshop on VLSI Signal Processing, San Diego, '90.
  • `Bit-Level Systolic Systems,' Int. Conf. Systolic Arrays, Killarney, IRELAND, '89.
  • `Systolic Array Design,' IEEE Workshop on VLSI Signal Processing, Monterey, '88.
  • `Array and Parallel Processing,' 20th Ann. Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, '86.
  • `Digital Signal Processing Theory I,' IEEE Workshop on VLSI Signal Processing, USC, Los Angeles, '86.
  • `Systolic Arrays,' Int. Conf. Acoustics, Speech, and Signal Processing, San Diego, '84.

SOCIETY

Chair

IEEE ASSP Society Technical Committee on VLSI, '83 -- '85 (Founding Chair).

Member

  • Association for Computing Machinery (ACM)
  • Senior member, Institute of Electrical and Electronics Engineers (IEEE):
    • Computer Society
    • Signal Processing Society
      • Advisory Board, TC on the Design & Implementation of Signal Processing Systems (DISPS) Formerly the TC on VLSI.
  • Upsilon Pi Epsilon


 cappello@cs.ucsb.edu 2009.04.27                                  805.893.4383