CS 154 Lab 3 : Pipelined MIC-1 Implemented in Quartus

Due: 23:59 5/27/2009.
Version 1
This lab will be graded interactively, sign-up sheets will be posted near the due date. An student who misses his/her group's grading time will receive a 0 for this assignment.

In this lab, you will add pipelining to the MIC-1 you built in Lab 2 (you must use *your* Lab 2 solution). You will separate the four subcycles of the original machine into pipeline stages, adding pipeline registers in the data and control paths between the stages. The four stages will be called:

  • IF - instruction fetch into MIR
  • ID - instruction decode and register read into A and B flip-flops
  • EX - ALU execute
  • MEM - memory read/write and register writeback

    Before you start building your circuit, carefully consider which clock-edge will be the active-edge for your pipeline registers, and which will be the active-edge for other registers. While you will be doing function simulation (unless you are doing the extra credit), there will still be "timing" issues related to the various registers.

    You will need to add hazard detection and data forwarding logic to the machine to allow correct operation. You will also need to worry about branch hazards. You MAY NOT add NOPs to your microcode. You must have your machine insert them dynamically.

    It is up to you what combination of stalls and forwarding you wish to use to make your machine operate correctly. Stalling is adequate for branch hazards, but EXTRA CREDIT will be given for branch prediction (see below).

    EXTRA CREDIT 1: (10 pts) Download your design onto the Altera hardware. Once again, you will need to test your design using timing simulation. If you plan on doing this extra credit, you must contact your TA no later than the on-time due-date to discuss it.

    EXTRA CREDIT 2: Implement branch prediction (choose only one).

    Last updated May 2009
    chong@cs.ucsb.edu