CS290N Extra-Performance Computer Architecture
Prof. Fred Chong
FQ 2006
Problem Set 11 (Architectural Vulnerability Factor - Susmit Biswas)

1. Why is device or circuit level modeling not suitable for soft error analysis?

2. What is the difference between soft error in logic elements and storage elements?

3. Is there any need to model soft error for predictors? Why?

4. How will soft error rate depend on memory latency?