CS290N Extra-Performance Computer Architecture
Prof. Fred Chong
SQ 2006
Problem Set 6 (Cache Missing for Fun and Profit - Bob Gilbert)
                                             
1. On the Intel Pentium 4 with Hyper-Threading processor, why is it a
   concern that threads share access to the memory caches?

2. Why does the L2-collision covert channel have significantly lower
   bandwidth than the L1-collision covert channel?

3. How can a change to the cache eviction policy affect the
   exploitation of these covert channels?

4. What help (if any) could the operating system lend to the closing
   of covert timing channels of this sort?