Synchroscalar is a tile-based architecture for embedded processing that is designed to provide the flexibility of DSPs while approaching the power efficiency of ASICs. We achieve this goal by providing high parallelism and voltage scaling while minimizing control and communication costs. Specifically, Synchroscalar uses columns of processor tiles organized into statically-assigned frequency-voltage domains to minimize power consumption. Furthermore, while columns use SIMD control to minimize overhead, data-dependent computations can be supported by extremely flexible statically-scheduled communication between columns.
John Oliver, Diana Franklin, Frederic T Chong, and Venkatesh Akella. ``Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture,'' to appear in Transactions on High-Performance Embedded Architectures and Compilers.
John Oliver, Ravishankar Rao, Jennifer Mankin, Michael Brown, Diana Franklin, Venkatesh Akella, and Frederic T. Chong. ``Tile Size Selection for Low-Power Tile-Based Architectures." In the ACM International Conference on Computing Frontiers, May 2006.
J. Oliver, R. Rao, D. Franklin, V. Akella, and F. Chong, "Synchroscalar: Evaluation of an Embedded, Multi-core Architecture for Media Applications," to appear in the Journal of Embedded Computing.
J. Oliver, R. Rao, P. Sultana, J. Crandall, E. Czernikowski, L. Jones, D. Franklin, V. Akella, and F. Chong, "Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor," International Symposium on Computer Architecture, ISCA-04, Munich, Germany, June 2004.
R. Rao, J. Oliver, P. Sultana, J. Crandall, E. Czernikowski, L. Jones, D. Copsey, D. Keen (Franklin), V. Akella, and F. Chong, "Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture," Power-Aware Computer Systems Workshop, in con-junction with MICRO-2003, December 2003.