Nagy Mostafa (nagy@cs.ucsb.edu)

I am a Ph.D. student at Computer Science Department, University of California, Santa Barbara. I received both my M.Sc. and B.Sc. degrees from Computer Science and Automatic Control Department, Faculty of Engineering, Alexandria University, Egypt in 2006 and 2003, respectively. I am currently working at Racelab under supervision of Prof. Chandra Krintz

Research

My broad area of research is adaptive runtime systems with focus on efficiently collecting information about executing programs (profiling). I am aiming to study performance profiling techniques suitable for resource-constrained devices.

Current Work

I am currently working towards passing my Major Area Exam (MAE). My work is about efficient performance profiling techniques with focus on path profiling. [Reading list: pdf doc]

Previous Work

March 2007 - Mono Profiling A course project for the CS 263, UCSB. Mono is the open-source version of .NET framework and is able to run on both Windows and Linux. We modified Mono source to be able to profile its garbage collector. Furthermore, we extended it to integrate with OProfile, a system-wide profiler. We updated Mono dynamic compiler to emit an image file that can be used later on by OProfile to match gathered samples against method bodies. We performed some analysis on the results and compared them with those obtained using Mono built-in sampling profiler.


January 2007 - Online DVD Store using Ruby on Rails A course project for the CS 290F, UCSB. An online DVD store website was built using Ruby on Rails. Site contents were populated from Amazon E-Commerce web service. Amazon EC-2 web service was used for hosting. Website ability to scale was measured by plotting the response time against the number of application servers used.


June 2006 -An FPGA-based Chip-Multiprocessor Model Implemented as part of my M.Sc. Thesis under supervision of Prof. Ahmed El-Mahdy, Alexandria University, Egypt. The aim was to build a chip-multiprocessor VHDL model based on the Jamaica architecture (Greg Wright, University of Manchester, UK). The model implemented consisted of 2-4 symmetric multi-threaded RISC processors with support for fine-grained threads and fast thread forking and switching mechanism. The model was mapped three times on three different FPGA devices and clock speed and space were measured for each case. The model was also benchmarked using micro benchmarks. For each benchmark, sequential and parallelized versions were run. The speed up obtained through parallelization was also measured.

Teaching

Classes I have TA'ed at UCSB:

• CS130b: Data Structures and Algorithms II (Winter 2007)
• CS153a: Hardware/Software Interface (Fall 2006)

Classes I have TA'ed at Faculty of Engineering, Egypt:

• Numerical Methods
• Discrete Mathematics
• Introduction to Programming
• Fundamentals of Digital Design
• Introduction to Computer Architecture

Other Interests

Being a computer nerd is not all I can do, I also have passion for:

• Listening to Classical Music
• Playing the Piano
• Music Theory
• Photography
• Arabic/English Literature