Welcome to the website of the UCSB Computer Architecture
and Embedded Systems Lab

Computer Architecture and Embedded Systems research will define with the way that future generations of computing machines will be organized, designed, and embedded into our lives. The UCSB ArchLab, directed by Professor Tim Sherwood, aims to push the frontiers of this research area by taking an interdisciplinary and cross-cutting approach. Advanced computer system design is not an island, but rather it sits between algorithms, operating systems, compilers, circuits, networks, and security; by looking at computer architecture and embedded systems through the eyes of it's application we can enact the biggest change. This is the basic philosophy of our lab.

Introspective Computing

Even today, software bugs are so damaging and widespread that they cost the U.S. economy alone an estimated $59.5 billion annually (more than half a percent of the US GNP). As our applications and software continue to grow in complexity, it is worth considering a processor with built-in support for introspection -- everywhere from the circuits to the software. Such a design could enable systems that monitor themselves for defects, that catch security violations as they occur, and optimize themselves over time. My lab has been been considering the use of novel technologies, such as 3D-Integration, to add introspection hardware in the last stages of processor fabrication. With a small amount of hardware support, we can help guide program profiling, direct processor reconfiguration, and enable new methods that track events both spatially and temporally. Portions of this work were selected by IEEE Micro as some of the top picks of 2004 (on phases) and 2006 (on 3d introspection)

Race Logic

We propose a novel computing approach, dubbed “Race Logic”, in which information, instead of being represented as logic levels, as is done in conventional logic, is represented as a timing delay. Under this new information representation, computations can be performed by observing the relative propagation times of signals injected into the circuit (i.e. the outcome of races). Race Logic is especially suited for solving problems related to the traversal of directed acyclic graphs commonly used in dynamic programming algorithms. The main advantage of this novel approach is that information processing (min-max and addition operations) can be very efficiently expressed through the manipulation of the natural delay chaining inherent to digital designs, which then results in superior latency, throughput, and energy efficiency. To verify this hypothesis, we designed several Race Logic implementations of a DNA global sequence alignment engine and compared it to the state-of-the-art conventional systolic array implementation. Our synthesized design shows that synchronous Race Logic is up to 4× faster when both approaches are mapped to a 0.5μm CMOS standard cell technology. At the same time the throughput for sequence matching per circuit area is about 3× higher at 5× lower power density for 20-long-symbol DNA sequences. In addition to the paper linked above, and summary can be found in our IEEE Micro Top Pick on "Abusing Hardware Race Conditions to do Useful Computation"

Provable Security Properties for Embedded Systems

Systems responsible for controlling aircraft, protecting a bank's master secret keys, or regulating access to extremely sensitive commercial or military information, all demand a level of assurance far beyond the norm. Creating these systems today is an incredibly expensive operation both in terms of time and money; and even assessing the assurance of the resulting system can cost upwards of $10,000 per line of code. Building upon my groups experience developing novel security methods for FPGAs [rcsec1, rcsec-cs-journal, rcsec-dt-journal, rcsecmoats, rcsec-recon-journal, rcsec-todaes-journal ], we have developed a novel method for building embedded systems that allow us to verify the integrity or secrecy of all information executing in that system. This includes safety from covert channels, information flows introduced during refinement, implicit flows, and even timing channels. The key to our approach is to verify properties of the both the hardware and the software down at the lowest level digital level of refinement -- at the individual Boolean logic gates. Specifically we developed a new logic discipline for security, {\it Gate-Level Information-Flow Tracking (GLIFT)} logic, and demonstrated its effectiveness by creating functional units, control logic, a new ISA, language, compiler, and fully synthesizable prototype CPU in this new logic [glift-cpu, glift-toppick, glift-lease ].

Network and Security Processing

A primary focus of Prof. Sherwood's research is designing new computer architectures specifically to be embedded into the network. Applications in this domain are throughput-driven, irregular, and bounded by the need for worst-case performance. These characteristics are not well supported by cache-heavy latency-intolerant traditional designs. The architecture we are developing takes advantage of many small, wide word, on-chip memories to rapidly traverse the large graph structures common to many security applications. In addition to the novel architecture work here, we also provide a set of memory models for modeling Ternary CAM (TCAM) power and delay tool that is simple to use, accurate and validated. It can help networking people and architects to explore various SRAM-TCAM hybrid algorithms and quantify the overhead and improvement.