Invited Chapters and Books

1. Peter R. Cappello and Kenneth Steiglitz.Unifying VLSI Array Design with Geometric Transformations. In C. Wu and Tse-yun Feng, editors, Tutorial: Interconnection Networks for Parallel and Distributed Processing, IEEE Computer Society Press, Aug. 1984 (reprinted conference article).
2. Peter R. Cappello et al., editors. VLSI Signal Processing, IEEE Press, Inc., New York, 1984.
3. Peter R. Cappello. Spacetime Transformations of Cellular Algorithms. In Earl E. Swartzlander, Jr., editor, Systolic Signal Processing Systems, pages 161--207, Marcel Dekker Inc., New York, NY., July 1987.
4. Peter R. Cappello and Kenneth Steiglitz.A VLSI Layout for a Pipelined Dadda Multiplier. In Earl E. Swartzlander, Jr., editor, Computer Arithmetic, II, pages 205--222, IEEE Computer Society Press, 1990, (reprinted journal article).
5. Grant Davidson, Peter R. Cappello, and Allen Gersho. Systolic Architecture for Vector Quantization. In H. Abut, editor, Vector Quantization, pages 499--512, IEEE Press, New York, 1990, (reprinted journal article).
6. Peter R. Cappello. Processor-Time Minimal Systolic Arrays. Chapt. 3 in Graham M. Megson, editor, Transformational Approaches to Systolic Design, pp. 53--76, Chapman Hall, Sep. 1993.
7. Peter Cappello, Omer Egecioglu, and Chris Scheiman. Processor-Time-Optimal Systolic Arrays. In Highly Parallel Computations, M. P. Bekakos (ed.), Advances in High Performance Computing Series, pp. 237 - 270, WIT Press, UK, 2001. Full paper (pdf).
8. Peter Cappello and Christopher James Coakley. A Development and Deployment Framework for Distributed Branch-and-Bound. Chapter 41 (41-1 - 41-11) in Approximation Algorithms and Metaheuristics, T. Gonzalez (ed.), CRC Press, May 2007.